Advanced Multithreading Architecture with Hardware Based Scheduling

FPGA based soft-processors are an attractive approach for embedded system engineering. Multithreading is proposed as the method to manage long latency events that are caused by I/O, off-chip memory and other shared resource accesses. However, most of the earlier multi-threaded soft-processors were based on conventional FPMT and CGMT architectures, which fall short for several reasons. In this paper, we propose a novel multithreading architecture for soft-processors that eliminates the thread switch penalty, while maintaining the single thread performance.