Title :
Technology impact analysis for 3D TCAM
Author :
Oh, Eun Chu ; Franzon, Paul D.
Author_Institution :
ECE Dept., North Carolina State Univ., Raleigh, NC, USA
Abstract :
In our previous work, 3D TCAMs were designed and evaluated with different 3D partitioning schemes showing that a 40% reduction in matchline interconnect capacitance, 21% power reduction, and 25% reduction in precharge time is achieved in TCAM memory array in 3-tier design based on MIT Lincoln Labs 3D IC process compared to a single-tier design. In this paper, we expand the exploration of the 3D TCAM design in various 3D IC technologies to show how the variations of technology parameters impact the benefits of 3D IC on TCAM. The impact of technology parameters including the number of wafer stacks, 3D via size, metal extension for 3D via alignment, and 3D via deposition order is evaluated in terms of interconnect capacitance and resistance in 3D TCAM designs.
Keywords :
content-addressable storage; integrated circuit interconnections; 3-tier design; 3D ternary content addressable memory; 3D via alignment; 3D via size; MIT Lincoln Labs 3D IC process; TCAM memory array; capacitance interconnection; metal extension; single-tier design; wafer stacks; Associative memory; Capacitance; Decoding; Driver circuits; Energy consumption; Integrated circuit interconnections; Logic; Metallization; Multilevel systems; Three-dimensional integrated circuits; 3D IC; 3D TCAM; 3D intertier via; 3D technology analysis; content addressable memory; low power TCAM; matchline capacitance; vertical interconnect;
Conference_Titel :
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-4511-0
Electronic_ISBN :
978-1-4244-4512-7
DOI :
10.1109/3DIC.2009.5306563
