Evaluation of fine grain 3-D integrated arithmetic units

Three dimensional (3-D) technologies have come under the spotlight to overcome limitations of conventional two dimensional (2-D) microprocessor implementations. However, the effect of 3-D integration with vertical interconnects in arithmetic units design is not well discussed yet. In this paper, aiming at clarifying the effectiveness of the 3-D integrated technology in arithmetic units design, fine grain 3-D integrated arithmetic units that aggressively employ vertical interconnects are designed and evaluated. This paper also presents a design strategy for 3-D integrated arithmetic units, which partitions a circuit into sub-circuits to fully exploit the benefit of 3-D technologies. The simulation results using practical through-silicon-vias (TSVs) show that the fine grain 3-D integrated arithmetic units with the proposed circuit partitioning policy have a potential to improve the performance of the future arithmetic units.