Title :
Analog VLSI circuits for learning rate adaptation in self-organizing neural networks
Author :
Sellami, L. ; Newcomb, W. ; Ferrandez, J.M. ; Rodellar, V. ; Gomez, P. ; Roa, L.
Author_Institution :
Dept. of Electr. Eng., US Naval Acad., Annapolis, MD, USA
Abstract :
We present analog VLSI circuits for the learning rate adaptation in self-organizing neural networks using the Mulier-Cherkassky learning rate adapted to the continuous-time case. The circuit design uses the solution of the Riccati equation as a basis for implementing the learning rate schedule
Keywords :
CMOS analogue integrated circuits; Riccati equations; VLSI; learning (artificial intelligence); neural chips; self-organising feature maps; statistical analysis; CMOS level shifter circuit; Kohonen feature maps; Mulier-Cherkassky learning rate; Riccati equation; analog VLSI circuits; self-organizing neural networks; statistical analysis; Circuits; Electronic mail; Intelligent networks; Neural networks; Neurons; Organizing; Pattern recognition; Riccati equations; Scheduling; Very large scale integration;
Conference_Titel :
Neural Networks Proceedings, 1998. IEEE World Congress on Computational Intelligence. The 1998 IEEE International Joint Conference on
Conference_Location :
Anchorage, AK
Print_ISBN :
0-7803-4859-1
DOI :
10.1109/IJCNN.1998.682325
