Time-multiplexed routing resources for FPGA design

Author

Chih-chang Lin ; Chang, D. ; Yu-Liang Wu ; Marek-Sadowska, M.

Author_Institution

Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA

fYear

1996

fDate

5-8 May 1996

Firstpage

152

Lastpage

155

Abstract

We propose a time-multiplexed routing architecture for SRAM based FPGAs. This can be implemented by having two programmable SRAMs for each routing connection. The goal of this approach is to alleviate the on-chip routing bottleneck, and to increase the range of circuit sizes which can be accommodated on a single chip. We consider a Xilinx 4000 style architecture with and without time-multiplexed routing. Our experimental results show that time-multiplexed routing can reduce the channel density by 30%. Also, sharing permutation equivalent LUTs between the time phases can result in a 14% reduction of the number of LUTs required to implement a design.

Keywords

circuit layout CAD; circuit optimisation; field programmable gate arrays; integrated circuit layout; logic CAD; network routing; random-access storage; table lookup; time division multiplexing; FPGA design; SRAM based FPGAs; Xilinx 4000 style architecture; channel density; circuit sizes; look-up tables; permutation equivalent LUTs; programmable SRAMs; time phases; time-multiplexed routing resources; Circuits; Field programmable gate arrays; Logic arrays; Phased arrays; Pins; Programmable logic arrays; Random access memory; Routing; Switches; Table lookup;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996

Conference_Location

San Diego, CA, USA

Print_ISBN

0-7803-3117-6

Type

conf

DOI

10.1109/CICC.1996.510532

Filename

510532