Performance scalability in ATM networks

In this work, the performance scalability of ATM functions in the B-ISDN framework is explored. The aim is to identify the potential bottlenecks in designing circuits for ATM systems and to evaluate the effect of these limitations on system performance. Dependency relationships are used to illustrate and analyse the designs,given varying degrees of parallelism. The data flow in the receiver and transmitter sections are analysed to identify the critical delay paths. The design considerations imposed by SONET framing are also discussed. Limitations imposed by AAL-5, which is the preferred ATM adaptation layer for data networks, are identified. Finally, the results are combined to establish an overall limit on performance