A single-chip low power DSP/RISC CPU with 0.25 μm CMOS technology

Author

Shikata, Takashi ; Kondou, Shinya ; Nose, Masanori ; Kuniyasu, Yoshio ; Naitoh, Mutsuhiro ; Suzuki, Hidetaka

Author_Institution

Fujitsu Ltd., Kanagawa, Japan

fYear

1998

fDate

11-14 May 1998

Firstpage

123

Lastpage

126

Abstract

We developed a PDC system LSI chip, which is embedded with a 16 bit fixed point DSP and a 32 bit RISC CPU by utilizing the latest 0.25 μm CMOS technology. The DSP part was designed specifically for the personal digital cellular (PDC) system, which makes it possible to perform Pitch Synchronous Innovation-Code Excited Linear Prediction (PSI-CELP) operations with 38 MIPS in one chip. Moreover, various techniques were applied to this device to achieve low power consumption; only 17 mA (0.34 mA/MIPS) at 1.8 V for a 50 MIPS operation on the DSP block

Keywords

CMOS digital integrated circuits; cellular radio; digital signal processing chips; large scale integration; linear predictive coding; microprocessor chips; reduced instruction set computing; speech codecs; telecommunication computing; transceivers; 0.25 micron; 1.8 V; 17 mA; 32 bit; 38 MIPS; 50 MIPS; CMOS technology; PDC system LSI chip; PSI-CELP operations; code excited linear prediction; embedded fixed point DSP; low power DSP/RISC CPU; personal digital cellular system; pitch synchronous innovation; single-chip DSP/RISC CPU; CMOS technology; Central Processing Unit; Digital signal processing; Digital signal processing chips; Energy consumption; Random access memory; Read only memory; Read-write memory; Reduced instruction set computing; Speech codecs;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.694920

Filename

694920