Enhanced FM0 decoder for UHF passive RFID readers using duty cycle estimations

This paper proposes a novel FM0 decoding technique for EPC Class 1 Generation 2 (Gen 2) UHF RFID readers. The proposed decoder overcomes the limitations of current implementations, which focus on correlation based decoding and require complex synchronization schemes. New rectangular wave symbols are derived from the FM0 stream and mapped to corresponding bit sequences using duty cycle estimations. Since the duty cycle approximated is independent of the received data rate, the proposed decoder is unaffected by the large +/- 22% data rate deviation and can decode the whole data rate range of 40kHz to 640kHz without changing the decoder structure. Furthermore, the characteristics of the rectangular wave symbols allow for early bit error detection prior to CRC computation. The duty cycle based decoder is prototyped on a Xilinx Virtex 5 FPGA and subsequent FPGA utilization data are presented and compared with a correlation-based scheme. BER measurements show that higher performance gains are achieved as the number of samples per symbol used for duty cycle estimations is increased.