The challenges and opportunities in GHz microprocessor design on 0.13 μm and beyond technologies

Author

Zhang, Kevin X.

Author_Institution

Intel Technol. & Res. Labs, Intel Corp., Hillsboro, OR, USA

Volume

2

fYear

2001

fDate

22-25 Oct. 2001

Firstpage

1102

Abstract

CMOS technology scaling continues to be the main driving force behind the advancement of high-performance microprocessors. As the feature size of CMOS transistors shrinks below 0.13 μm, and gate delay is rapidly reduced below 20 ps, the frequency of leading edge microprocessors has well exceeded the 1 GHz barrier now. The combination of both transistor and frequency scaling has created many new challenges in high-speed CPU design. This paper addresses many of the key technical challenges in today´s multi-GHz CPU design, including low-power and low-leakage design, high-speed and skew tolerant latching strategy, on-die high-speed cache, and robust design against soft-error. Potential design solutions are discussed.

Keywords

CMOS digital integrated circuits; high-speed integrated circuits; integrated circuit design; leakage currents; low-power electronics; microprocessor chips; 0.13 micron; 20 ps; CMOS GHz microprocessor design; CMOS technology scaling; CMOS transistor feature size; design solutions; frequency scaling; gate delay; high-performance microprocessors; high-speed CPU design; high-speed skew tolerant latching strategy; low-power low-leakage design; on-die high-speed cache; soft-error robustness; transistor scaling; CMOS technology; Central Processing Unit; Clocks; Delay; Digital circuits; Frequency; Microprocessors; Power supplies; Robustness; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th International Conference on

Print_ISBN

0-7803-6520-8

Type

conf

DOI

10.1109/ICSICT.2001.982091

Filename

982091