Test point insertion based on path tracing

Author

Touba, Nur A. ; McCluskey, Edward J.

Author_Institution

Center for Reliable Comput., Stanford Univ., CA, USA

fYear

1996

fDate

28 Apr-1 May 1996

Firstpage

2

Lastpage

8

Abstract

This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than using probabilistic techniques for test point placement, a path tracing procedure is used to place both control and observation points. Rather than adding extra scan elements to drive the control points, a few of the existing primary inputs to the circuit are ANDed together to form signals that drive the control points. By selecting which patterns the control point is activated for, the effectiveness of each control point is maximized. A comparison is made with the best previously published results for other test point insertion methods, and it is shown that the proposed method requires fewer test points and less overhead to achieve the same or better fault coverage

Keywords

VLSI; automatic testing; built-in self test; fault diagnosis; integrated circuit testing; logic testing; probability; timing; BIST; VLSI; circuit-under-test; fault coverage; insertion methods; logic testing; path tracing; primary inputs; probabilistic techniques; test point insertion; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Control systems; Hardware; Logic circuits; Observability; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1996., Proceedings of 14th

Conference_Location

Princeton, NJ

ISSN

1093-0167

Print_ISBN

0-8186-7304-4

Type

conf

DOI

10.1109/VTEST.1996.510828

Filename

510828