A new physical timing model for bipolar NTL circuits

Author

Wu, Chug-Yu ; Wu, Tain Shun

Author_Institution

Nat. Chiao Tung Univ., Hsin-Chu, Taiwan

fYear

1988

fDate

12-13 Sep 1988

Firstpage

223

Lastpage

226

Abstract

Based on current-domain large-signal equivalent circuits, a new physical timing model for bipolar nonthreshold logic (NTL) circuits is developed. Through extensive comparisons with SPICE simulation results, it is found that the maximum error is 25% for the NTL inverters with different operating currents, capacitance loads, device parameters, and input excitation waveforms not deviating much from characteristic waveforms. Moreover, the consumed CPU time and memory in calculations are much less than those in full transient simulations

Keywords

bipolar integrated circuits; circuit analysis computing; equivalent circuits; integrated logic circuits; logic gates; NTL inverters; SPICE simulation; bipolar nonthreshold logic circuits; capacitance loads; current-domain large-signal equivalent circuits; input excitation waveforms; operating currents; physical timing model; Circuit simulation; Design optimization; Equivalent circuits; Inverters; Logic circuits; Logic devices; Logic gates; SPICE; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar Circuits and Technology Meeting, 1988., Proceedings of the 1988

Conference_Location

Minneapolis, MN

Type

conf

DOI

10.1109/BIPOL.1988.51084

Filename

51084

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2219334