Enhancing realistic fault secureness in parity prediction array arithmetic operators by IDDQ monitoring

Parity prediction arithmetic operator schemes have been widely studied in the past. Recently, it has been demonstrated that this prediction scheme can achieve Fault-Secureness in arithmetic circuits for stuck-at and stuck-open faults. In this paper it is shown that the detection capability improves if a current monitoring technique is used in conjunction with the parity prediction scheme. With this scheme the fault-secure property extends to bridging faults. The technique is validated by the topological design and SPICE simulation of a multiplier circuit