CMOS high-speed I/Os - present and future

Author

Lee, M. J Edward ; Dally, William J. ; Farjad-Rad, Ramin ; Ng, Hiok-Tiaq ; Senthinathan, Ramesh ; Edmondson, John ; Poulton, John

Author_Institution

Velio Commun. Inc., Milpitas, CA, USA

fYear

2003

fDate

13-15 Oct. 2003

Firstpage

454

Lastpage

461

Abstract

High-speed I/O circuits, once used only for PHYs, are now widely used for intra-system signaling as well because of their bandwidth, power, area, and cost advantages. This technology enables chips with over 1 Tb/s of I/O bandwidth today and over 10 Tb/s of bandwidth by 2010 as both signaling rates and number of high-speed I/Os increase with process scaling. Key technologies that enable this growth in I/O performance include low-jitter clock circuits and equalized signaling. An analysis of clock jitter and channel interference suggests that signaling rates should track transistor performance to rates of at least 40 Gb/s over boards, back-planes, and short-distance cables.

Keywords

CMOS integrated circuits; high-speed integrated circuits; interference (signal); scaling circuits; synchronisation; system-on-chip; timing jitter; CMOS high-speed I/O circuit; I/O bandwidth; I/O transistor performance; channel interference; intra-system equalized signaling rate; low-jitter clock circuits; process scaling; short-distance cables; Bandwidth; CMOS technology; Circuits; Clocks; Costs; Interference; Jitter; Performance analysis; Signal analysis; Signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2003. Proceedings. 21st International Conference on

ISSN

1063-6404

Print_ISBN

0-7695-2025-1

Type

conf

DOI

10.1109/ICCD.2003.1240940

Filename

1240940