A bit-serial architecture for H.264/AVC interframe decoding

The H.264/AVC is the most recent standard of video compression. In this paper, an original and efficient architecture of inter prediction block in an H.264/AVC decoder is presented. It is shown that the bit-serial arithmetic can be successfully used for interpolation filter implementation and the resulting architecture is fully pipelined. The inter prediction module was implemented in Verilog HDL and synthesized and then tested on Xilinx Virtex IV family devices. The simulation results indicate that the proposed bit-serial architecture of interpolation filter is very efficient and clock frequency close to the image sampling frequency is enough to perform image reconstruction.