DocumentCode
2224628
Title
CFG in sub-graph matching based HW/SW Co-Design
Author
Tang, Lei ; Wei, Shaojun ; Qiu, Yulin
Author_Institution
Microelectron. R&D Center, Acad. Sinica, Beijing, China
fYear
2001
fDate
2001
Firstpage
171
Lastpage
174
Abstract
In this paper, a method considering CFG\´s effect on the costs of sub-graph matching based HW/SW system is proposed. First, a discussion of all kinds of effects generated by CFG in sub-graph matching based co-design is made. Next, an algorithm called "Grade Every Sub-Graph of a DFG According to Its Execution Frequency Decided by CFG" (GESG) is proposed unifying all these effects. At last, delay cost function of sub-graph matching based HW/SW system is modified according to GESG. Experiments and their results are reported and discussed
Keywords
flow graphs; hardware-software codesign; GESG algorithm; control flow graph; delay cost function; hardware/software co-design; sub-graph matching; Circuits; Control systems; Cost function; Delay; Flow graphs; Frequency; Hardware; High level synthesis; Microelectronics; Research and development;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982524
Filename
982524
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