Integrated floorplanning and power supply planning

The power supply planning is very important for high performance VLSI design. An algorithm is proposed, which deals with the design and optimization of tree-based power/ground network in the BBL-based VLSIs. The object of the algorithm is to minimize the routing area used by a power tree. This paper presented an integrated floorplanning and power supply planning algorithm for BBL-based VLSI, which minimizes the chip area used by both blocks and power networks. The algorithm solves two problems. The first is the overestimation problem: only routing area used by the power tree is reserved. The second is the constraints dissatisfactory problem: if no feasible power tree satisfies the constraints in a floorplan, the floorplan will be changed. Experimental results on MCNC benchmarks show promising performance