• DocumentCode
    2226403
  • Title

    CMOS scaling and non-silicon opportunities

  • Author

    Nishi, Yoshio

  • Author_Institution
    Dept. of Electr. Eng., Stanford Univ., Stanford, CA
  • fYear
    2006
  • fDate
    Jan. 30 2006-Feb. 1 2006
  • Firstpage
    6
  • Lastpage
    12
  • Abstract
    Scaling trend of CMOS, coupled with possibility of new channel materials, metal gate/ high k gate stack and source/drain structures is discussed, followed by several possibilities and opportunities for non-silicon devices including new material based non-volatile memory devices.
  • Keywords
    CMOS memory circuits; CMOS scaling; channel materials; high k gate stack; nonsilicon opportunities; nonvolatile memory devices; source-drain structures; Costs; Energy management; III-V semiconductor materials; Inorganic materials; Leakage current; Lithography; MOSFETs; Nonvolatile memory; Power system management; Radio frequency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nano CMOS, 2006 International Workshop on
  • Conference_Location
    Mishima
  • Print_ISBN
    978-1-4244-0603-6
  • Type

    conf

  • DOI
    10.1109/IWNC.2006.4570972
  • Filename
    4570972
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2226403