Automated transistor sizing algorithm for minimizing spurious switching activities in CMOS circuits

In this paper a new approach for minimizing glitches in the combinational parts of static CMOS circuits is presented. Delay balancing is applied in order to guarantee synchronously arriving signal slopes at the inputs of the logic gates. Thus, glitching can be avoided. The delay of a logic gate depends directly on the transistor sizes, i.e. the channel-widths and -lengths (W and L). Specific variation of the transistor sizes allows one to equalize different path delays without influencing the total propagation delay of the circuit. Besides the delay, the total capacitance and the short-circuit power consumption of a circuit also depend on the transistor sizes. In order to take this fact into account when sizing transistors for delay balancing, the method is formulated as a multiobjective optimization problem, where the path delay differences and the power consumption are the design objectives. A program GliMATS for automated circuit optimization has been implemented. Experimental results show that significant power savings can be achieved with this method