FIR digital filter implementation using flattened coefficient

In this paper, we present a new method to reduce the number of adders and registers in FIR digital filters. Few efforts have been taken for reducing the number of registers in filters, while a lot of methods have been developed to decrease the number of adders in the past decade. This paper presents a novel method to cut down the number of registers without loss of critical path delay by mixing the direct-form filter with the transversal one. Two adder-sharing structures, one for small area and the other for high data rate, are proposed. For low power consumption, each adder is shared only one time in these structures. As a result, proposed area-efficient adder-sharing structure can reduce area (15%), and power consumption (44%). Also, a new throughput efficient structure can decrease area (3%), delay (24%), and power consumption (25%)