DocumentCode
2227428
Title
Low power design in 100 MHz embedded SRAM
Author
Dong-Hui, Wang ; Jing, Qiu ; Yungang, Li ; Chaohuan, Hou
Author_Institution
Inst. of Semicond., Acad. Sinica, Beijing, China
fYear
2001
fDate
2001
Firstpage
599
Lastpage
602
Abstract
A low power design method is used in a 100 MHz embedded SRAM. The embedded SRAM used in an FFT chip is divided into 16 blocks. Two-level decoders are used and only one block can be selected at one time by tristate control circuits, while other blocks are set at stand-by. The SRAM cell has been optimized and the cell area has been minimized at the same time
Keywords
CMOS memory circuits; SRAM chips; circuit optimisation; embedded systems; integrated circuit layout; low-power electronics; 100 MHz; 100 MHz embedded SRAM; FFT chip; SRAM cell optimization; cell area minimization; low power design; multi-stage static CMOS decoding; multiple threshold voltage CMOS; tristate control circuits; two-level decoders; variable threshold voltage CMOS; Capacitance; Circuits; Decoding; Design methodology; Energy consumption; Power amplifiers; Power dissipation; Power system reliability; Random access memory; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982635
Filename
982635
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