DocumentCode
2227463
Title
How to generate tests using semi-formal technique: industrial experiences
Author
Dushina, Julia ; Benjamin, Mike ; Geist, Daniel
Author_Institution
STMicroelectron., Bristol, UK
fYear
2001
fDate
2001
Firstpage
607
Lastpage
611
Abstract
This paper resulted from the successful application of semi-formal test generation techniques on two industrial designs: a block of a new high performance digital signal processors and a block of a new 64-bit processor core. We describe the developed test generation methodology that should be applicable to a wide range of designs
Keywords
digital signal processing chips; integrated circuit testing; logic testing; microprocessor chips; storage management chips; 64-bit processor core; DMAC architecture; ST50 direct memory access controller; high performance digital signal processors; industrial designs; semi-formal test generation techniques; test generation methodology; Data structures; Digital signal processors; Explosives; Gold; Routing; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2001. Proceedings. 4th International Conference on
Conference_Location
Shanghai
Print_ISBN
0-7803-6677-8
Type
conf
DOI
10.1109/ICASIC.2001.982637
Filename
982637
Link To Document