Retargetable Netlists Generation and Structural Synthesis Based on a Meta Hardware Description Language: Melasy+

We are developing a compiler system, Melasy+, which is at a level higher than compiler systems of various model-checking and hardware description languages. Melasy+ describes a single code and allows model-checking and operation tests on an actual machine via a code generator for each language. In this study, for an XML intermediate representation code that was output by Melasy+, the elements of the target circuit are analyzed to generate a detailed list and then static analysis of the circuit is carried out. The net list after regeneration is a digraph and the meta-information obtained in the analysis is given to its edge.