Influence of sampling jitter on discrete time receiver

In software defined radio (SDR), implementation of RF front-end and analog-to-digital converter (ADC) is an important issue. One type of new schemes proposed for SDR is discrete time receiver (DTR), which processes analog signal directly. In the DTR architecture, the received signal is sampled at radio frequency (RF) and channel selection and demodulation are carried out in the digital domain. This architecture achieves reduction of on-chip components and enables one-chip receiver. However, in this architecture, the sampling jitter generated from phase noise of phase locked loop (PLL) may deteriorate the performance. In this paper, the phase noise of the PLL is modeled and the influence of the phase noise to the DTR is analyzed. Moreover, the performance of the DTR is evaluated in terms of modulation schemes and signal bandwidth