Optimized design of OPA in focal plane array readout circuits

Author

Jun, Gao ; Wengao, Lu ; Tianyi, Zhang ; Lijiu, Ji

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

fYear

2001

fDate

2001

Firstpage

865

Lastpage

868

Abstract

This paper describes the optimized design of two kinds of operational amplifier (OPA) in the column readout circuit and output buffer of focal plane array (FPA) circuit, based on 1.2 μm double poly double metal (DPDM) CMOS process. Hspice simulation shows that the OPA for column readout circuit works with GBW of 0.9 MHz, power of 35 μW, settling time of 3 μs. The OPA in output buffer can work at GBW of 12 MHz, power of 1.8 mW, settling time of 144 ns, which may support the dimension of FPA as large as 400*400 pixels at 30 frames/sec

Keywords

CMOS analogue integrated circuits; circuit optimisation; focal planes; operational amplifiers; readout electronics; 0.9 MHz; 1.2 μm double poly double metal CMOS; 1.2 micron; 12 MHz; 160000 pixel; 3 mus; 30 frames/sec; 35 muW; 400 pixel; Hspice simulation; column readout circuit; focal plane array; operational amplifier; optimized design; output buffer; power 35 μW; power of 1.8 mW; settling time 3 μs; settling time of 144 ns; CMOS process; Capacitance; Circuit noise; Circuit simulation; Design optimization; Feedback; Microelectronics; Operational amplifiers; Stability; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2001. Proceedings. 4th International Conference on

Conference_Location

Shanghai

Print_ISBN

0-7803-6677-8

Type

conf

DOI

10.1109/ICASIC.2001.982701

Filename

982701