Title :
Synthesizing data paths with arithmetic self-test
Author :
Stroele, Albrecht P.
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
In many circuits, adders and subtracters are readily available. Together with some other modules of the circuit, these arithmetic units can be configured to accumulators, which are useful as test pattern generators and test response compactors. This arithmetic built-in self-test has the potential to avoid the problems of conventional test register insertion. But not all circuits are well-suited. This paper shows how the high-level synthesis process can be guided to data path structures that provide favorable conditions for arithmetic self-test without detrimental effects on area and speed. The presented assignment procedure leads to data paths that include a variety of accumulator structures and paths to and from the modules to be tested
Keywords :
built-in self test; circuit CAD; digital arithmetic; high level synthesis; integrated circuit design; integrated circuit testing; logic testing; accumulator structures; arithmetic BIST; arithmetic built-in self-test; arithmetic self-test; assignment procedure; data paths; datapath synthesis; high-level synthesis process; test pattern generators; test response compactors; Adders; Arithmetic; Automatic testing; Built-in self-test; Circuit synthesis; Circuit testing; High level synthesis; Integrated circuit interconnections; Registers; Test pattern generators;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856254
