Synthesizing data paths with arithmetic self-test

In many circuits, adders and subtracters are readily available. Together with some other modules of the circuit, these arithmetic units can be configured to accumulators, which are useful as test pattern generators and test response compactors. This arithmetic built-in self-test has the potential to avoid the problems of conventional test register insertion. But not all circuits are well-suited. This paper shows how the high-level synthesis process can be guided to data path structures that provide favorable conditions for arithmetic self-test without detrimental effects on area and speed. The presented assignment procedure leads to data paths that include a variety of accumulator structures and paths to and from the modules to be tested