Title :
Notice of Retraction
Full-Custom Design of a 16-Bit Multiplier for 0.5um Processing
Author :
Liu Zhizhe ; Zhong Shunan
Author_Institution :
Dept. of Electron. Eng., Beijing Inst. of Technol., Beijing, China
Abstract :
Notice of Retraction
After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE´s Publication Principles.
We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper.
The presenting author of this paper has the option to appeal this decision by contacting TPII@ieee.org.
This paper described a 16-bit multiplier. Modified booth algorithm and the Wallace tree were used to reduce the carry save partial product to sum and carry vectors, a carry look-ahead adder was designed to convert the sum and carry vectors to final format. Based on the research of the algorithm and the full-custom back end implementation, this multiplier is expected to achieve high performance, low power dissipation, small chip area, and low cost. After simulation of post place, the operating cycle time of the multiplier is 24.3ns under the ss simulation state for 0.5um processing.
Keywords :
adders; digital arithmetic; integrated circuit design; trees (mathematics); 16-bit multiplier; Wallace tree; carry look-ahead adder; full-custom design; low power dissipation; modified booth algorithm; size 0.5 mum; word length 16 bit; Added delay; Adders; Algorithm design and analysis; Circuits; Costs; Design engineering; Information science; Page description languages; Paper technology; Power dissipation;
Conference_Titel :
Information Science and Engineering (ICISE), 2009 1st International Conference on
Conference_Location :
Nanjing
Print_ISBN :
978-1-4244-4909-5
DOI :
10.1109/ICISE.2009.608
