HiBRID-SoC: a system-on-chip architecture with two multimedia DSPs and a RISC core

Author

Friebe, L. ; Stolberg, H.-J. ; Berekovic, M. ; Moch, S. ; Kulaczewski, M.B. ; Dehnhardt, A. ; Pirsch, P.

Author_Institution

Inst. fur Mikroelektronische Syst., Hannover Univ., Germany

fYear

2003

fDate

17-20 Sept. 2003

Firstpage

85

Lastpage

88

Abstract

The HiBRID-SoC integrates three fully programmable processor cores, each optimized towards a particular class of algorithm: the HiPAR-DSP for DSP oriented functions, the macroblock processor for block oriented algorithms, and the stream processor for bitstream processing. Dedicated interface units for SDRAM, serial Flash, and host system access are connected via a 64 bit AMBA AHB system bus with the processor cores. Dual-port memories between the processor cores facilitate fast data and control information exchange between the cores. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm², and operates at 160 MHz.

Keywords

digital signal processing chips; integrated circuit design; logic design; multimedia computing; reduced instruction set computing; system buses; system-on-chip; 0.18 micron; 160 MHz; 64 bit; ARB system bus interface; DSP oriented functions; HiBRID-SoC; RISC core; SDRAM; SoC; bitstream processing; block oriented algorithms; control information exchange; data information exchange; dual-port memories; fully programmable processor cores; host system access; macroblock processor; multimedia DSP; multimedia signal processing applications; serial Flash; stream processor; system-on-chip architecture; Application software; Computer architecture; Digital signal processing; Hardware; MPEG 4 Standard; Multimedia systems; Reduced instruction set computing; Streaming media; System buses; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]

Print_ISBN

0-7803-8182-3

Type

conf

DOI

10.1109/SOC.2003.1241468

Filename

1241468