A new fully integrated CMOS phase-locked loop with low jitter and fast lock time

Author

Fouzar, Y. ; Sawan, M. ; Savaria, Y.

Author_Institution

Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada

Volume

2

fYear

2000

fDate

2000

Firstpage

253

Abstract

In this paper we describe a novel PLL circuit design. The proposed topology is based on two loops: the conventional fine loop and a new coarse loop. The fine tuning loop which includes a phase-frequency detector, a charge pump and a differential voltage controlled oscillator (unity feedback PLL) is rather slow. However the coarse tuning loop reacts faster and accelerates convergence. It also ensures a better stability, a shorter locking time, and as a result, a low jitter is obtained, as well as a lower sensitivity to power supply variations

Keywords

CMOS integrated circuits; circuit stability; circuit tuning; convergence; jitter; mixed analogue-digital integrated circuits; phase locked loops; CMOS phase-locked loop; PLL circuit design; charge pump; coarse tuning loop; convergence; differential VCO; fast lock time; fine tuning loop; fully integrated CMOS PLL; low jitter; phase-frequency detector; power supply variations sensitivity reduction; stability; unity feedback PLL; voltage controlled oscillator; Charge pumps; Circuit optimization; Circuit synthesis; Circuit topology; Jitter; Phase detection; Phase frequency detector; Phase locked loops; Tuning; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856309

Filename

856309