Title :
Low complexity VLSI implementation of a joint successive interference cancellation with interleaving scheme
Author :
Wong, Bob Ka-Man ; Tsui, Chi-ying ; Cheng, Roger S K
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., China
Abstract :
The performance of wideband code division multiple access (WCDMA) can be severely degraded as the number of users increases due to the increase in interference. Multi-user detection is a scheme, which can cancel the interference generated by other users and hence can improve the system capacity. Recently a joint successive interference cancellation with interleaving (JSICI) scheme has been proposed for multi-user detection. However the complexity of the scheme is very high. In this paper, we propose a low complexity architecture which can implement this JSICI scheme efficiently in VLSI. Also low power features are proposed
Keywords :
VLSI; code division multiple access; interference suppression; interleaved codes; land mobile radio; JSICI; interleaving scheme; joint successive interference cancellation; low complexity VLSI; low power features; multi-user detection; system capacity; wideband code division multiple access; Degradation; Delay estimation; Interference cancellation; Interleaved codes; Multiaccess communication; Multiple access interference; Multiuser detection; Signal generators; Transmitters; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on
Conference_Location :
Geneva
Print_ISBN :
0-7803-5482-6
DOI :
10.1109/ISCAS.2000.856337
