Title :
Interconnect estimation for segmented FPGA architectures
Author :
Kannan, Parivallal ; Bhatia, Dinesh
Author_Institution :
Erik Jonsson Sch. of Eng. & Comput. Sci., Texas Univ., Dallas, TX, USA
Abstract :
Most modern FPGAs have a segmented architecture, with routing tracks of varying lengths. No interconnect estimation method is available for such architectures. We propose a new method that produces reliable estimates for segmented FPGA architectures on both global and local levels. We compare our estimates with the detailed routing results produced by standard routing tools in the VPR design suite.
Keywords :
field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; network routing; FPGA interconnect estimation; global estimates; local level estimates; routing tools; routing track lengths; segmented FPGA architectures; Computer architecture; Computer science; Design methodology; Field programmable gate arrays; Integrated circuit interconnections; Modems; Process design; Reliability engineering; Routing; Timing;
Conference_Titel :
SOC Conference, 2003. Proceedings. IEEE International [Systems-on-Chip]
Print_ISBN :
0-7803-8182-3
DOI :
10.1109/SOC.2003.1241528
