DocumentCode :
2231852
Title :
A novel 14 ∼ 170 MHz All digital delay locked loop with ultra fast locking for SoC applications
Author :
Moorthi, S. ; Meganathan, D. ; Prasad, N. Krishna ; Perinbam, J. Raja Paul
Author_Institution :
Dept. of Electr. & Electron. Eng., Nat. Inst. of Technol., Trichy, India
fYear :
2011
fDate :
22-24 Sept. 2011
Abstract :
A delay locked loop (DLL) is a feedback control system that equalizes the phase of two delayed copies of the same clock signal. The DLL is useful for compensating the clock distribution delays that arise in many system configurations. An all-digital delay-locked loop (ADDLL) is presented to achieve wide range of operation, fast lock, Harmonic-Free and process immunity. The paper proposes a Modified Variable Successive Approximation Register-controlled (MVSAR) algorithm to achieve the fast-locking property, closed-loop operation and performing binary search without harmonic-locking issue. The fast locking of proposed MVSAR is verified by comparing it with the existing architectures. The proposed ADDLL is implemented at system level with standard cells and it has good portability over different processes. It is synthesized using TSMC 0.18 μm, six-metal technology. The lock range (operating frequency range) of the ADDLL is 14MHz to 170 MHz and occupied an area (physical design) of 142*142 Sq.μm (0.020164 Sq.mm).
Keywords :
delay lock loops; system-on-chip; SoC applications; all digital delay locked loop; closed-loop operation; fast-locking property; frequency 14 MHz to 170 MHz; harmonic-locking issue; modified variable successive approximation register-controlled algorithm; process immunity; six-metal technology; size 0.18 mum; ultra fast locking; Approximation algorithms; Approximation methods; Clocks; Delay; Delay lines; Detectors; Radiation detectors; All Digital Delay Locked Loop (ADDLL); Modified VSAR (MVSAR); Variable Successive Approximation Register (VSAR); clock de-skew;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Conference_Location :
Trivandrum
Print_ISBN :
978-1-4244-9478-1
Type :
conf
DOI :
10.1109/RAICS.2011.6069276
Filename :
6069276
Link To Document :
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