A CMOS low-power, high-speed, asynchronous comparator for synchronous rectification applications

A novel approach for the design of an asynchronous comparator implemented in standard digital CMOS technology for power supply applications is presented. The 1 mV sensitivity comparator is designed for asynchronous event detection, featuring a multi-stage topology for power efficiency and minimum propagation delay. It also contains a mixed-mode offset compensation architecture that allows full compensation in a single cycle. The comparator has been successfully used in the design of a very high frequency, 300 mA multi-mode PWM/PSM (Pulse Width Modulation/Pulse Skipping Mode) buck converter. The comparator is able to operate with a supply voltage as low as 2.4 V. Operating with a 3.6 V supply, under typical operating conditions, the comparator features a 19 ns delay consuming 161 μW