A 1W Class-D Audio Power Amplifier in a 0.35μm CMOS Process

A fully integrated class-D audio power amplifier for mobile applications is presented. The amplifier is realized in a 0.35 μm CMOS process featuring 3.3 V and 5 V transistors. To reduce the out-of-band noise generation, possibly eliminating the need of an output filter, the double sided natural sampling (DSNS) pulse width modulation (PWM) scheme is used at a designed carrier frequency of 384 kHz. By using a 5 V full bridge, a maximum output power of 1 W (rms) was measured in a 7.5Ω load at 1% THD+N and an efficiency of 80%. The THD+N was 0.24% at 500 mW output, and 0.15% in minimum. The total chip area is 2.55 mm² including pads. This chip was designed and simulated with Cadence IC design tools as a student project in the course IC Project and Verification at Lund University.