High Level Synthesis of Parallel Tile Processing Units with non-uniform memory accesses

This paper presents an automatic method to generate a TPU (tile processing unit). The TPU processes blocks of data according to a user-defined functionality and access data through an optimized memory access controller. A TPU has different levels of parallelism which are achieved jointly through data and computation tiling. For a given application and a user defined level of parallelism, a set of possible data partitioning is explored and the solutions with the minimal internal memory and the best temporal performances are chosen. In this work, the automatic method is used as a front-end of the high-level synthesis. For each chosen solution a whole synthesizable C-model is generated.