A 2 V 1.6 GHz BJT phase-locked loop

Author

Chen, Wei-Zen ; Wu, Jieh-Tsorng

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1998

fDate

11-14 May 1998

Firstpage

563

Lastpage

566

Abstract

This paper describes the design of a BJT phase-locked loop (PLL) for ΣΔ fractional-N frequency synthesis applications. Implemented in a 0.8 μm BiCMOS technology, the PLL can operate up to 1.6 GHz, while consuming 225 mW of power from a single -2 V supply. The LC-tuned negative-resistance variable-frequency oscillator is integrated on the same chip. A low-voltage current-mode logic circuit configuration is used to minimize phase jitter and achieve low-voltage operation. Die size is 4300×4000 μm²

Keywords

BiCMOS integrated circuits; UHF integrated circuits; frequency synthesizers; jitter; mixed analogue-digital integrated circuits; phase locked loops; sigma-delta modulation; transceivers; ΣΔ fractional-N frequency synthesis; 0.8 micron; 1.6 GHz; 2 V; 225 mW; BJT phase-locked loop; BiCMOS technology; LC-tuned negative-resistance VFO; LV current-mode logic circuit configuration; PLL; low-voltage operation; phase jitter; variable-frequency oscillator; Circuits; Frequency control; Frequency modulation; Frequency synthesizers; Oscillators; Phase frequency detector; Phase locked loops; Phase modulation; Phase noise; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.695041

Filename

695041