A 1.8 V/3.5 mA 1.1 GHz/300 MHz CMOS dual PLL frequency synthesizer IC for RF communications

Author

Lo, Steve ; Olgaard, Christian ; Rose, Dennis

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1998

fDate

11-14 May 1998

Firstpage

571

Lastpage

574

Abstract

This paper describes the design of a low-voltage phase-locked loop (PLL) in a dual frequency synthesizer IC. The dual frequency synthesizes IC integrates a 1.1 GHz RF PLL, a 300 MHz IF PLL, a circuit for the Colpitt´s oscillator, and two 8-bit DACs. The RF PLL, with an external VCO and loop filter, exhibits close-in phase noise of -72 dBc/Hz at 150 Hz away from the carrier and spurious suppression of better than -65 dBc over a wide charge pump tuning range of 0.2 V to Vdd-0.4 V. The whole chip consumes 3.5 mA at 1.8 V power supply. This chip was fabricated in a 0.35 μm digital CMOS process with typical V_tn and V_tp of 0.6 V and 0.8 V respectively

Keywords

CMOS integrated circuits; UHF integrated circuits; frequency synthesizers; mixed analogue-digital integrated circuits; phase locked loops; radio equipment; 0.35 micron; 1.1 GHz; 1.8 V; 3.5 mA; 300 MHz; CMOS dual PLL frequency synthesizer IC; Colpitt oscillator; DACs; IF PLL; RF PLL; RF communications; low-voltage PLL; phase-locked loop; Charge pumps; Circuit synthesis; Filters; Frequency synthesizers; Integrated circuit synthesis; Phase locked loops; Phase noise; Radio frequency; Radiofrequency integrated circuits; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-4292-5

Type

conf

DOI

10.1109/CICC.1998.695043

Filename

695043