A nonlinear programming and local improvement method for standard cell placement

A new VLSI design procedure incorporating an iterative construction and a local improvement method is presented to deal with standard cell placement. This approach uses no partitioning techniques which are common in the placement approaches. Experimental results on benchmarks and other circuits up to 15059 cells indicate that the new approach yields placements that are comparable to those obtained by TimberWolf 5.1 and is 3-5 times faster than TimberWolf 5.1