A multilink ATM switch capable of supporting two priority classes

The switch employs a pre-emptive priority mechanism in which delay sensitive traffic (class 1) can preempt delay insensitive traffic (class 2) in input buffers when competing for the same output port. The architecture uses a simplified Batcher Banyan Switch (SBBS) fabric which requires a simple hardware structure, running a 4-phase algorithm on a slot-by-slot basis. Performance studies have shown that the switch is capable of providing low delay for class 1 traffic and a reasonably good performance for class 2 traffic using a large number of links per link group. The performance of class 1 is unaffected by an increasing class 2 load