Parity prediction method for on-line testing of a Barrel-shifter

This paper addresses the problem of on-line testing of floating-point computing circuits. The problem is connected with the use of the truncated operations in the part of mantissas processing. The arithmetic shift performed on a Barrel-shifter is the most often used truncated operation. Known approaches to on-line testing of the Barrel-shifter are based on duplication of the truncated operation or on its restoring to a long shift. This makes of the error detection scheme more complex. Known residue checking method, which implements a prior computation of the check results for all causes of a shift reduces the check hardware overhead from square dependence on an operand size to a linear one. However this method requires to perform a series of complex operations for generating and processing of the check codes by modulo. We propose the parity prediction method that significantly simplifies the error detection scheme of a Barrel-shifter by using simple check operations.