Overlay through metal to CMP: product demands, process challenges, review of contribution variables and improvement options

The rapid evolution of ICs to meet consumer demands of increased speed, circuit density, performance, cost, yield and reliability has been fuelled by smaller and tighter photolithography groundrules (GRs). The linewidth (pattern critical dimension; CD) GR component is shrinking almost exactly per the long-term forecasts of industry experts; most manufacturing plants are now operating at 0.5 um or below using i-line (with perhaps process, photoresist material, lens, reticle or other enhancements) or shorter wavelengths (DUV→VDUV & XRay) to achieve sub-half-micron sized images. However, the overlay (pattern registration) component actual performance is beginning to fall off the one third linewidth rule of thumb target estimator used by most circuit designers. The current cost effective overlay is felt to be about 0.15 um, somewhat larger than the 0.12 um GR specification for 0.35 um technology. This project began do to this void, as well as to overlay imparting the greater influence on edge to edge yield||reliability performance between layers. The situation in the Back End of Line (BEOL; wiring) is a much greater challenge as alignment typically must be, done through metal film(s) to a potentially planarized or asymmetric chemically mechanically polished (CMP) alignment target. We have evaluated several process parameters (via fill, CMP, blanket metal, photoresist), align mark designs, sizes and types (up vs. down; Kerf vs. Global edge), alignment system and setup parameters. This paper reviews the results of many options one has when faced with tight overlay design rules and the ultimate challenge: Through Metal→CMP Alignment