Hardware Computation of the PageRank Eigenvector

A hardware solver, implemented on an FPGA, for calculating the Page Rank eigenvector using the Power method is described. The critical operation is a very large sparse matrix by vector multiplication (SMVM). However, we show that the SMVM can be replaced with a pattern adder (a term coined to denote SMVM without multiplication), and a dense element by element vector multiplication, thus simplifying the calculation and improving performance. The system was tested for correctness and performance using a set of Internet Adjacency matrices. Performance data for Virtex 2 and Virtex 5 implementations are presented and an average performance improvement of 180% over a state of the art general purpose processor was achieved by the Virtex 5 implementation.