A Hardware-Efficient Frequency Domain Correlator Architecture for Acquisition Stage in GPS

A frequency domain correlator (FDC) with low-complexity architecture is proposed. This signal processing module is part of FFT-based acquisition stage of a global position system (GPS). The FDC is based on a single reconfigurable core capable of computing both decimation in frequency radix-2 (DIF-2) fast Fourier transform (FFT) and decimation in time radix-2 (DIT-2) inverse fast Fourier transform (IFFT). The proposed FDC reuses the reconfigurable core together with appropriate decimation choice, providing an improvement in resource management while avoiding any additional reorder data hardware. Additionally, the FDC architecture shows a great flexibility due to three levels of parameterization which allows to fix the number of complex input samples, data width and word format. The architecture has been implemented in Altera Cyclone II and Xilinx Virtex II Pro for N-points correlation with different word lengths. The simulation and synthesis results shows that the FDC is suitable for performing acquisition stage in GPS, enabling its utilization in software define radios.