Impact of thermal budget on dopant-segregated (DS) metal S/D gate-all-around (GAA) PFETs

Author

Akarvardar, K. ; Rodgers, M. ; Kaushik, V. ; Johnson, C.S. ; Ok, I. ; Ang, K.-W. ; Stamper, H. ; Bennett, S. ; Franca, D. ; Rao, M. ; Gausepohl, S. ; Hobbs, C. ; Kirsch, P. ; Jammy, R.

Author_Institution

GlobalFoundries, Sunnyvale, CA, USA

fYear

2012

fDate

23-25 April 2012

Firstpage

1

Lastpage

2

Abstract

Low temperature (T ≤ 480C after gate stack) DS Metal S/D GAA PFETs were fabricated and benchmarked to devices with S/D activation anneal (SDAA). It is shown that when DS implantation precedes gate spacer formation, devices without SDAA have higher peak G_m and I_Dsat, however also higher I_off than their counterparts with SDAA. Fabricated low-thermal-budget GAA PFETs with TiN/HfO₂ gate and NiPtSi S/D achieve I_Dsat = 0.8 mA/um and I_on/I_off >; 2000 for VGS = -1.5 V, V_DS = -1 V, and 100 nm nanowire length.

Keywords

annealing; field effect transistors; nanowires; semiconductor doping; DS implantation; NiPtSi; S/D activation anneal; TiN-HfO₂; dopant-segregated metal S/D gate-all-around PFET; gate spacer formation; low temperature DS metal S/D GAA PFET; nanowire; size 100 nm; thermal budget; voltage -1 V; voltage -1.5 V; Annealing; Implants; Logic gates; MOSFETs; Metals; Silicides; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on

Conference_Location

Hsinchu

ISSN

1930-8868

Print_ISBN

978-1-4577-2083-3

Type

conf

DOI

10.1109/VLSI-TSA.2012.6210131

Filename

6210131