Title :
Lowering the drawbacks of slowing down di/dt and dv/dt of insulated gate transistors
Author :
Sawezyn, H. ; Idir, N. ; Bausière, R.
Author_Institution :
Lab. d´´Electrotechnique et d´´Electronique de Puissance, Univ. des Sci. et Technol., Lille, France
Abstract :
Introducing intermediate levels into the gate control voltage of isolated gate transistors allows to slow down current or voltage rising into the switching device, thus reducing overcurrent due to reverse recovery of the associated diode, and resulting in electromagnetic interferences. But the same reduction may be achieved simply by increasing the gate resistance value into the control circuit. In this paper, it is shown that slowing down the current or voltage rate-of-rise by intermediate voltage level leads to better performances in terms of delay times and switching losses than higher gate resistance value.
Keywords :
electromagnetic interference; field effect transistor switches; power MOSFET; power semiconductor switches; semiconductor device measurement; semiconductor device models; semiconductor device testing; EMI; delay times; gate control voltage; gate resistance; insulated gate transistors; overcurrent reduction; switching device; switching losses;
Conference_Titel :
Power Electronics, Machines and Drives, 2002. International Conference on (Conf. Publ. No. 487)
Print_ISBN :
0-85296-747-0
DOI :
10.1049/cp:20020176