DocumentCode
2238396
Title
Understanding and improving SILC behavior under TDDB stress in full gate-last high-k/metal gate nMOSFETs
Author
Jo, Minseok ; Kang, Chang Young ; Ang, Kah-Wee ; Huang, Jeff ; Kirsch, Paul ; Jammy, Raj
Author_Institution
SEMATECH, Austin, TX, USA
fYear
2012
fDate
23-25 April 2012
Firstpage
1
Lastpage
2
Abstract
Stress-induced leakage current (SILC) behavior in full gate-last (FGL) high-k/metal gate devices was evaluated and compared to gate-first (GF) devices. To improve SILC characteristics, Zr was introduced into the high-k bulk region. Incorporating Zr can reduce SILC in both FGL and GF devices by suppressing trap generation in the high-k bulk region under time-dependent dielectric breakdown (TDDB) stress. However, the interfacial layer quality can be a critical SILC issue in FGL devices.
Keywords
MOSFET; electric breakdown; high-k dielectric thin films; leakage currents; zirconium; FGL device; SILC behavior; TDDB stress; Zr; full gate-last high-k/metal gate nMOSFET; gate-first devices; interfacial layer quality; stress-induced leakage current; time-dependent dielectric breakdown; trap generation; Electric breakdown; High K dielectric materials; Leakage current; Logic gates; Metals; Stress; Zirconium;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location
Hsinchu
ISSN
1930-8868
Print_ISBN
978-1-4577-2083-3
Type
conf
DOI
10.1109/VLSI-TSA.2012.6210154
Filename
6210154
Link To Document