Title :
A 20nm low-power triple-gate multibody 1T-DRAM cell
Author :
Gamiz, F. ; Rodriguez, N. ; Cristoloveanu, S.
Author_Institution :
Dept. Electron., Univ. of Granada, Granada, Spain
Abstract :
The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.
Keywords :
DRAM chips; embedded systems; low-power electronics; nanoelectronics; N-core depletion; N/P body partition; electron current; embedded systems; hole concentration; hole storage; low-power triple-gate multibody 1T-DRAM cell; memory window; nondestructive reading; size 20 nm; Bridge circuits; Charge carrier processes; Current density; Doping; Logic gates; Random access memory; Tunneling;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210166
