Title :
Optimizing state-of-the-art 28nm core/SRAM device performance by cryo-implantation technology
Author :
Yang, C.L. ; Li, C.I. ; Lin, G.P. ; Chen, W.J. ; Tsai, C.H. ; Huang, Y.S. ; Fu, C. ; Lu, T.Y. ; Wang, H.Y. ; Hsu, B.C. ; Huang, C.T. ; Chan, M. ; Wu, J.Y. ; Cheng, Y.C. ; Cheng, O. ; Guo, B.N. ; Lu, S. ; Gossmann, H.-J. ; Colombeau, B. ; Chen, I.C.
Author_Institution :
United Microelectron. Corp. (UMC), Tainan, Taiwan
Abstract :
In this paper, we have demonstrated that cryogenic implantation applied to source and drain (SD) extension, pocket/halo and SD formation offers advantages for higher core and SRAM driving current and one order lower Ioff bulk (Ioffb) leakage in NMOS with reduced SRAM defectivity. Atomistic Kinetic Monte Carlo (KMC) modeling confirms that the cryo-implantation has enabled a unique control of active Boron and point defect distribution in the channel/halo region of NMOS.
Keywords :
MOS memory circuits; Monte Carlo methods; SRAM chips; KMC modeling; NMOS; SD formation; atomistic kinetic Monte Carlo modeling; core/SRAM device; cryo-implantation technology; drain extension; pocket/halo; size 28 nm; source extension; Annealing; Boron; Carbon; Implants; Junctions; MOS devices; Random access memory;
Conference_Titel :
VLSI Technology, Systems, and Applications (VLSI-TSA), 2012 International Symposium on
Conference_Location :
Hsinchu
Print_ISBN :
978-1-4577-2083-3
DOI :
10.1109/VLSI-TSA.2012.6210167
