A CMOS Current-Reused Transceiver with Stacked LNA and Mixer for WPAN

Author

Yoo, Sang-Sun ; Yun, Seok-Oh ; Shin, Soo-Hwan ; Yoo, Hyung-Joun

Author_Institution

Sch. of Eng., Inf. & Commun. Univ., Daejeon

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

33

Lastpage

36

Abstract

A low power transceiver is designed in 0.25 mum CMOS technology. Designed transceiver is composed of CMOS PA and low-IF receiver architecture for high integration. To reduce the power dissipation, current-reused topology is used in Rx and up-conversion mixer. And, the simulated power consumption of PA is minimized by optimizing the size of power cells. The power consumptions are 31 mW and 69 mW for Rx and Tx paths, respectively, with 2.5 V supply voltage. Voltage conversion gain of designed receiver is varied from 11.5 to 27.5 dB. Output power is 14.7 dBm with 40 % of PAE at P_1dB, and phase noise of QVCO is -122 dBc/Hz@1MHz. These performances are sufficient for WPAN applications such as Zig-Bee and Bluetooth

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF mixers; UHF power amplifiers; low noise amplifiers; low-power electronics; personal area networks; transceivers; 0.25 micron; 11.5 to 27.5 dB; 2.5 V; 31 mW; 40 percent; 69 mW; Bluetooth; CMOS current-reused transceiver; CMOS power amplifier; CMOS technology; WPAN; Zig-Bee; low power transceiver; low-IF receiver architecture; stacked LNA; up-conversion mixer; Bluetooth; CMOS technology; Circuits; Costs; Energy consumption; Linearity; Radio frequency; Topology; Transceivers; Voltage; Bluetooth; WPAN; Zig-Bee; current-reuse; low power; stack; transceiver;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342289

Filename

4145325