VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System

Author

Yoshizawa, Shingo ; Miyanaga, Yoshikazu

Author_Institution

Graduate Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

93

Lastpage

96

Abstract

This paper presents a VLSI implementation of a high throughput MIMO-OFDM system in wireless communications. We explore the optimum parameters in a new packet OFDM frame by expanding the IEEE802.11a standard. The proposed system provides a maximum of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2 times 2 MIMO scheme. The proposed system is implemented into hardware according to a full-pipelined architecture. In the MIMO detection circuit, we adopt a low latency architecture to satisfy the timing constraint required for real-time MIMO detection. In a 90-nm CMOS technology, the system performing MMSE-V-BLAST detection has 3.9 millions in logic gates and consumes 584 mW in power dissipation

Keywords

CMOS integrated circuits; MIMO communication; OFDM modulation; VLSI; logic gates; wireless LAN; 584 mW; 600 Mbit/s; 80 MHz; 90 nm; CMOS technology; MIMO; OFDM; VLSI; detection circuit; logic gates; pipelined architecture; wireless communication system; Bandwidth; Baseband; CMOS logic circuits; CMOS technology; Hardware; MIMO; OFDM; Throughput; Very large scale integration; Wireless communication; MIMO; OFDM; VLSI; wireless communication;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342304

Filename

4145340