A Development and Validation Platform for Communication SOC Design

Author

Sun, YuChen ; Huang, ChingYao

Author_Institution

Dept. of Electron. Eng., National Chiao Tung Univ., HsinChu

fYear

2006

fDate

4-7 Dec. 2006

Firstpage

101

Lastpage

104

Abstract

This paper introduces a development and validation platform that combines hardware modeling and communication system simulation. This platform enables the use of a single platform for multiple purposes throughout a communication system design, including system simulation, software development and hardware modeling. Besides providing cycle accuracy hardware model, the platform is integrated with a multi-device simulation environment. Based on the platform, designers could complete protocol analysis and system simulation in a single stage. The platform is useful for the designs of communication components whose behaviors are highly coupled with transmission medium and other parallel components. This paper presents the basic components and their design strategies

Keywords

integrated circuit design; software engineering; system-on-chip; communication SOC design; communication system simulation; development platform; hardware modeling; multidevice simulation environment; protocol analysis; software development; validation platform; Analytical models; Couplings; Design engineering; Design methodology; Hardware; Nanoelectronics; Process design; Programming; Protocols; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on

Conference_Location

Singapore

Print_ISBN

1-4244-0387-1

Type

conf

DOI

10.1109/APCCAS.2006.342324

Filename

4145342